Azemard, Nadine: search on Z-Library

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1

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4644 || Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs

Azémard, Nadine, Svensson, Lars

Year:

2007

Language:

english

File:

PDF, 282 KB

english, 2007

2

[IEEE 2006 13th IEEE International Conference on Electronics, Circuits and Systems - Nice, France (2006.12.10-2006.12.13)] 2006 13th IEEE International Conference on Electronics, Circuits and Systems - Request-skip adders : CMOS standard cell data dependent adders

Perrot, Robin, Azemard, Nadine, Maurine, Philippe

Year:

2006

Language:

english

File:

PDF, 1.40 MB

english, 2006

3

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4148 || Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters

Vounckx, Johan, Azemard, Nadine, Maurine, Philippe

Year:

2006

Language:

english

File:

PDF, 467 KB

english, 2006

4

[IEEE 2012 IEEE Faible Tension Faible Consommation (FTFC) - Paris, France (2012.06.6-2012.06.8)] 2012 IEEE Faible Tension Faible Consommation - Statistical cells timing metrics characterization

Wu, Zeqin, Maurine, Philippe, Azemard, Nadine, Ducharme, Gilles

Year:

2012

Language:

english

File:

PDF, 7.23 MB

english, 2012

5

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4148 || Top Verification of Low Power System with “Checkerboard” Approach

Vounckx, Johan, Azemard, Nadine, Maurine, Philippe

Year:

2006

Language:

english

File:

PDF, 51 KB

english, 2006

6

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4148 || Methodology for Dynamic Power Verification of Contactless Smartcards

Vounckx, Johan, Azemard, Nadine, Maurine, Philippe

Year:

2006

Language:

english

File:

PDF, 617 KB

english, 2006

7

Editorial

Nadine Azemard, Philippe Maurine, Johan Vounckx

Journal:

Integration, the VLSI Journal

Year:

2008

Language:

english

File:

PDF, 73 KB

english, 2008

8

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4644 || A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling

Azémard, Nadine, Svensson, Lars

Year:

2007

Language:

english

File:

PDF, 430 KB

english, 2007

9

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4148 || Low-Power Adaptive Bias Amplifier for a Large Supply-Range Linear Voltage Regulator

Vounckx, Johan, Azemard, Nadine, Maurine, Philippe

Year:

2006

Language:

english

File:

PDF, 304 KB

english, 2006

10

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4148 || A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits

Vounckx, Johan, Azemard, Nadine, Maurine, Philippe

Year:

2006

Language:

english

File:

PDF, 448 KB

english, 2006

11

[IEEE 2010 8th IEEE International NEWCAS Conference (NEWCAS) - Montreal, QC, Canada (2010.06.20-2010.06.23)] Proceedings of the 8th IEEE International NEWCAS Conference 2010 - SSTA with delay correlations

Wu, Zeqin, Maurine, Philippe, Azemard, Nadine, Ducharme, Gilles

Year:

2010

Language:

english

File:

PDF, 1.72 MB

english, 2010

12

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4644 || Clock Distribution Techniques for Low-EMI Design

Azémard, Nadine, Svensson, Lars

Year:

2007

Language:

english

File:

PDF, 389 KB

english, 2007

13

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4644 || Logic Style Comparison for Ultra Low Power Operation in 65nm Technology

Azémard, Nadine, Svensson, Lars

Year:

2007

Language:

english

File:

PDF, 500 KB

english, 2007

14

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4148 || Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications

Vounckx, Johan, Azemard, Nadine, Maurine, Philippe

Year:

2006

Language:

english

File:

PDF, 276 KB

english, 2006

15

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation || Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism

Vounckx, Johan, Azemard, Nadine, Maurine, Philippe

Year:

2006

Language:

english

File:

PDF, 784 KB

english, 2006

16

Review—Energy Autonomous Wearable Sensors for Smart Healthcare: A Review

Dahiya, Abhishek Singh, Thireau, Jerome, Boudaden, Jamila, Lal, Swatchith, Gulzar, Umair, Zhang, Yan, Gil, Thierry, Azemard, Nadine, Ramm, Peter, Kiessling, Tim, O'Murchu, Cian, Sebelius, Fredrik, Til

Journal:

Journal of The Electrochemical Society

Year:

2020

Language:

english

File:

PDF, 1.10 MB

english, 2020

17

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4644 || Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates

Azémard, Nadine, Svensson, Lars

Year:

2007

Language:

english

File:

PDF, 304 KB

english, 2007

18

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4644 ||

Azémard, Nadine, Svensson, Lars

Year:

2007

Language:

english

File:

PDF, 23.05 MB

english, 2007

19

[IEEE Technology (ICICDT) - Grenoble, France (2010.06.2-2010.06.4)] 2010 IEEE International Conference on Integrated Circuit Design and Technology - Voltage scaling and body biasing methodology for high performance hardwired LDPC

Moubdi, Nabila, Maurine, Philippe, Wilson, Robin, Azemard, Nadine, Engels, Sylvain, Rolindez, Luis, Heinrich, Vincent

Year:

2010

Language:

english

File:

PDF, 257 KB

english, 2010

20

[IEEE 2020 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS (DTIP) - Lyon, France (2020.6.15-2020.6.26)] 2020 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS (DTIP) - Stretchable Strain Sensors for Human Movement Monitoring

Dahiya, Abhishek Singh, Gil, Thierry, Azemard, Nadine, Thireau, Jerome, Lacampagne, Alain, Todri-Sanial, Aida, Charlot, Benoit

Year:

2020

File:

PDF, 256 KB

2020

21

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4148 || Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling

Vounckx, Johan, Azemard, Nadine, Maurine, Philippe

Year:

2006

Language:

english

File:

PDF, 228 KB

english, 2006

22

[IEEE 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Bremen, Germany (2016.9.21-2016.9.23)] 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Physical description and analysis of doped carbon nanotube interconnects

Liang, Jie, Zhang, Liuyang, Azemard-Crestani, Nadine, Nouet, Pascal, Todri-Sanial, Aida

Year:

2016

Language:

english

File:

PDF, 1.27 MB

english, 2016

23

Delay-correlation-aware SSTA based on conditional moments

Zeqin Wu, Philippe Maurine, Nadine Azemard, Gilles R. Ducharme

Journal:

Microelectronics Journal

Year:

2012

Language:

english

File:

PDF, 959 KB

english, 2012

24

[IEEE 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Platja d'Aro, Spain (2018.7.2-2018.7.4)] 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management

Kheirallah, Rida, Galliere, Jean-Marc, Azemard, Nadine, Ducharme, Gilles

Year:

2018

File:

PDF, 560 KB

2018

25

[IEEE 2015 International Workshop on CMOS Variability (VARI) - Salvador, Brazil (2015.9.1-2015.9.4)] 2015 International Workshop on CMOS Variability (VARI) - Energy study for 28nm FDSOI technology

Kheirallah, Rida, Azemard, Nadine, Ducharme, Gilles

Year:

2015

Language:

english

File:

PDF, 972 KB

english, 2015

26

[IEEE Technology (ICICDT) - Grenoble, France (2010.06.2-2010.06.4)] 2010 IEEE International Conference on Integrated Circuit Design and Technology - Computing delay correlations in SSTA

Wu, Zeqin, Maurine, Philippe, Azemard, Nadine, Ducharme, Gille

Year:

2010

Language:

english

File:

PDF, 226 KB

english, 2010

27

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4148 || Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology

Vounckx, Johan, Azemard, Nadine, Maurine, Philippe

Year:

2006

Language:

english

File:

PDF, 667 KB

english, 2006

28

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4148 ||

Vounckx, Johan, Azemard, Nadine, Maurine, Philippe

Year:

2006

Language:

english

File:

PDF, 13.66 MB

english, 2006

29

[IEEE APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) - Macao, China (2008.11.30-2008.12.3)] APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - SSTA considering switching process induced correlations

Wu, Zeqin, Maurine, Philippe, Azemard, Nadine, Ducharme, Gille

Year:

2008

Language:

english

File:

PDF, 616 KB

english, 2008

30

[IEEE 2017 IEEE International Conference on Rebooting Computing (ICRC) - Washington, DC (2017.11.8-2017.11.9)] 2017 IEEE International Conference on Rebooting Computing (ICRC) - Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic

Jeanniot, Nicolas, Pillonnet, Gael, Nouet, Pascal, Azemard, Nadine, Todri-Sanial, Aida

Year:

2017

Language:

english

File:

PDF, 2.28 MB

english, 2017

31

SPIE Proceedings [SPIE International Symposium on Microelectronics and Assembly - Singapore, Singapore (Monday 27 November 2000)] Design, Modeling, and Simulation in Microelectronics - Delay-bound determination for path constraint satisfaction

Azemard, Nadine, Aline, Michel, Auvergne, Daniel, Courtois, Bernard, Demidenko, Serge N., Lau, Lee Y.

Year:

2000

Language:

english

File:

PDF, 73 KB

english, 2000

32

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 4644 || Design and Test of Self-checking Asynchronous Control Circuit

Azémard, Nadine, Svensson, Lars

Year:

2007

Language:

english

File:

PDF, 483 KB

english, 2007

33

[IEEE 2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) - Budapest, Hungary (2015.4.19-2015.4.22)] 2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems - Statistical energy study for 28nm FDSOI devices

Kheirallah, Rida, Galliere, Jean-Marc, Todri-Sanial, Aida, Azemard, Nadine, Ducharme, Gilles

Year:

2015

Language:

english

File:

PDF, 1.40 MB

english, 2015

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